Appendix A. Low-Cost Manufacturing Technology for the Fabrication of Amorphous Silicon Detectors

Digital detector integrated circuits are fabricated with amorphous silicon (a-Si) semiconductor layers for full-field imaging of large areas. Unlike single crystal silicon, a-Si layers can cover large areas without the need for stitching artifacts associated with lost spaces.

As indicated in Figure A1, the a-Si detector consists of a scintillator layer that converts incident X-ray energy to light and a photosensitive array that converts light into electrical charges. The photosensitive array is made up of picture elements (pixels) sized at 100–200 microns. Each pixel contains a photodiode that absorbs light from the scintillator and generates and stores electrical charges and a field-effect transistor (FET) that serves to isolate each pixel element and acts as a switch to convey electrical charges to external electronics for readout. Read-out electronics circuitry converts charges from each pixel to voltage signals for image processing and display. The entire array of more than a million pixels can be read and converted to a composite digital representation in less than a second.

Figure A1. Principles of Amorphous Silicon Detector

MANUFACTURING PROCESS

Photosensitive panels are fabricated as multiple layers of thin film deposited on a glass substrate. Photolithography is used for pattern formation. As indicated in Figure A2, each layer is built up via successive process steps:

• Deposition of a-Si thin film and insulating and conducing layers and coating with photoresist.
• Exposure to UV or ultraviolet light around masks.
• Development or removal of photoresist impacted by UV.
• Etching to remove layers around masks.
• Removal of the remaining photoresist.
• Deposition of the next layer.

The original GE process, prior to ATP funding, uses approximately 300 process steps and 11-mask photolithography to fabricate large area a-Si panels for medical applications. It starts with the deposition of the FET layer, followed by the deposition of the diode layer, and is completed with the deposition of the scintillator layer.

• Mask 1: Process begins with metal deposition for FET gates and scan lines.
• Mask 2: a-Si layer is deposited by plasma enhanced chemical vapor deposition.
• Mask 3: FET openings (vias) are cut through dielectric layer.
• Mask 4: Metal layers are deposited, patterned, and etched.
• Mask 5: Protective or passivation layer is deposited and patterned.
• Masks 6 and 7: a-Si layers are deposited and diode island is masked and etched.
• Mask 8: Diode passivant is deposited.
• Mask 9: Insulating layer applied to provide isolation from underlying structures.
• Mask 10: Common biasing contacts are deposited and patterned.
• Mask 11: Third passivating layer is deposited and removed in contact region.

Figure A2. Thin Film Processing: Depositing, Patterning, and Etching of Multiple Layers

The final step during baseline fabrication is a vapor phase deposition of cesium iodide (CsI) scintillator layer to convert X-ray energy to light. CsI is deposited to form microscopic columns or needles with their long axis normal to the substrate resulting in anisotropic properties (highly scattering to light propagating parallel to the substrate and transmissive to light normal to the substrate). CsI columns form miniature light traps that conduct light to the underlying a-Si imager with a minimum of lateral spreading.

The ATP-funded LCM process uses a different design than the baseline process. First, there is a reversal in process order whereby the deposition of the diode island precedes the deposition of the FET. Second, several fabrication steps, originally kept separate to optimize different aspects of device performance, are combined into dual or multiuse layers.

• Mask 1: Process begins with metal deposition for FET gates and scan lines.
• Mask 2: Diode fabrication begins with deposition of a-Si and indium tin oxide (ITO) layers.
• Mask 3: a-Si diode island is masked and etched.
• Mask 4: FET a-Si island is deposited, patterned, and the silicon layers are etched.
• Mask 5: Openings (vias) are cut to the bottom electrode.
• Mask 6: Metal layers are deposited, patterned, and etched.
• Mask 7: Protective barrier is deposited and removed in the contact regions.

Device fabrication is completed with the deposition of a CsI scintillator layer, using the identical process for baseline fabrication.

ACCOMPLISHMENTS OF ATP-FUNDED PROJECT

The ATP-funded process innovation resulted in fewer mask steps (seven versus eleven) and fewer total process steps (200 versus 300). This was accomplished through interleaved fabrication of the following dual or multiuse layers:

• Gate metal layer for scan line, FET gate, and bottom contact.
• FET dielectric layer for FET gate, diode sidewall passivation, and common electrode insulation.
• Barrier dielectric layer for FET sidewall passivation and protection barrier.
• ITO layer for diode and contact pads to drive electronics.

• Elimination of labor intensive test and repair steps for fabrication throughput advantage and improved data line repair capability intrinsic in device structure.
• Electronic noise reduction in data lines without additional process complexity.

• Reaching an acceptable compromise in FET and diode deposition temperatures.
• Identifying gate metals with acceptable sidewall slope after the etch.
• Optimizing FET island etch for selectivity to gate dielectric removal.
• Contact finger design for electronic bonding.

COST REDUCTION FROM LOW-COST PROCESS

The defect-free yield from the LCM process is equivalent to the original GE process prior to ATP funding. However, the production yield from LCM will be higher as fewer process step and lower mask count reduce processing time and cost. An equipment utilization model (see Table A1) was used to estimate LCM cost reduction relative to the original process. The model simulated six equipment clusters and  verified that reduction in mask count very closely scales with reduced process cost at about 25 to 30 percent.

As an additional advantage from the ATP-funded LCM process, reduced processing times on specific equipment clusters are expected to eliminate four of six future bottlenecked processes. Removing production bottlenecks from the fabrication process will:

• Eliminate or delay need for capacity expansion ($10 million avoided cost).
• Eliminate or delay physical disruptions associated with capacity expansion.

Table A1. Projected Equipment Utilization for a-Si Detector Fabrication

REMAINING TECHNICAL ISSUES

While the LCM process has been demonstrated as technically feasible, it is still considered developmental and “all risks have not been fully retired” (Giambattista 2001). The following areas require additional work:

• Particle contamination can limit yield impact of mask count reductions.
• Gate metal etch profile for the bimetallic gate structure is difficult to optimize and control. 
• Too much light hitting the FET can causes leakage in the data lines. There is a need to install a light block to protect the FET.

Order of magnitude resource requirements to resolve the remaining technical issues were estimated at several FTE’s (full time equivalent positions) of engineering effort and requiring access to some production capacity to conduct engineering runs for a period of up to 24 months.

Return to Table of Contents or go to Appendix B. Case Study Calculations.

Date created: April 25, 2003
Last updated: August 2, 2005

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