NIST Advanced Technology Program
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ATP Public Meeting Announcement
Semiconductor Lithography

November 20, 1997
The Park Plaza Hotel San Francisco
1177 Airport Boulevard, Burlingame, CA

(located five minutes south of San Francisco Int'l Airport)

About the Advanced Technology Program

NIST's Advanced Technology Program (ATP) provides competitive, cost-shared awards for industry to develop high-risk, enabling technologies with broad-based economic benefit. ATP seeks to help industry fill the gap between basic research and product development, and to invest in technology that would not be developed in a competitive time frame without government cost-sharing. Along with general competitions, which are open to proposals from all technical areas, ATP is also funding a series of "focused programs" with specific business and technical goals.

Background

The continuing reduction in cost per function in the semiconductor industry has been driven largely by reduction in feature sizes, which in turn has been possible through advances in semiconductor lithography.

Optical lithography has been the technology of the semiconductor industry for more than 30 years. This technology is expected to take the semiconductor feature sizes down to 0.18 micron and maybe down to 0.13 micron. To achieve smaller feature sizes, the semiconductor industry will need other imaging technologies.

The lithography equipment market is at present dominated by two Japanese companies, Nikon and Canon. To establish themselves as market leaders for lithography equipment for the next generation and beyond, U.S. companies have to dominate in the post-deep UV lithography technologies.

In order to meet the needs of the industry, research on new imaging technologies is under way in several laboratories around the world. The technologies include X-Ray Lithography, Extreme Ultraviolet Lithography, Electron Beam Lithography, and Ion Beam lithography. A preferred technology area may not emerge until late 1999.

Each of these alternative technologies, however, needs several common technologies that will support future semiconductor lithography. These include mask technologies, resist technologies, optical element fabrication technologies, metrology, alignment systems, safety, etc. An ATP focused program could address these common needs of the semiconductor lithography industry for < = 0.13 m m geometries for 2003 and beyond.

Purpose

Because a significant number of technology ideas have been submitted to ATP through white papers and phone calls in the area of lithography, ATP is seeking industry's input to determine whether a focused program is warranted. This ATP workshop is being held to determine the level of interest in a focused program in lithography technologies, the strength of the justification for such a program, and the appropriate scope of such a program. Representatives from companies or groups of companies, technical and trade associations, academic institutions, non-profit research institutions, and government laboratories are invited to this workshop to define the program, and provide feedback on how ATP can make an impact in this area. Participation is expected from equipment developers, metrology system developers, process developers, and users.

Participants will help to address the following key criteria for selecting program areas:

  • Potential U.S. economic impact, including the credibility of the program's proposed pathways to economic growth, the importance of the existing or potential sector affected, and the probability of subsequent commercialization;
  • Good technical ideas that are "cutting edge," high risk, strategically important, and based on sound scientific and technical concepts;
  • Strong industry commitment to participate, including breadth and depth of interest and willingness to share costs and to work with the government and other partners;
  • Opportunity for the ATP to make a major difference by supporting work that is unique or complementary to other industrial and government efforts, that offers timely and significant acceleration of research progress, and that requires a critical mass of funding.
The ATP will hold a one-day workshop on semiconductor lithography for interested parties on November 20, 1997, at The Park Plaza Hotel San Francisco. The formal meeting is from 11:00 a.m. to 5:00.p.m. There will also be informal discussion meetings from 9 a.m. to 11 a.m. and from 5 p.m. until 7:00p.m. The theme of the workshop is, "Defining an ATP focused program in semiconductor lithography technologies for the 21st century."

No formal registration is necessary. The agenda includes two sessions: Session One will develop the topics for discussions in Session Two, through brief presentations from SEMATECH, NIST, and all interested industrial participants. The specifics of the presentations should include technologies that would benefit the future imaging techniques. In this session, an ATP Introduction will be presented as well. Session Two will be roundtable discussions to define a possible program.


Workshop Information

Accommodations

    Park Plaza Hotel San Francisco -1-800-437-7275

List of nearby hotels in the area:

San Francisco Airport Hilton
1-800-932-3322

Best Western El Rancho Inn
(next to Airport)
1-800-826-5500

Hyatt Regency San Francisco Airport
1-800-233-1234

Crowne Plaza SF Airport
1-800-227-6963

Travelodge San Francisco Airport South
1-800-578-7878

Grosvenor Hotel
(One mile north of SFO International Airport)
1-800-722-7141

Ramada San Francisco Airport North
1-800-272-6232

Transportation

To reach the Hotel:

From the airport, take the complimentary shuttle - or proceed south on Highway 101 (the Bayshore Freeway) to the second exit (Broadway/Burlingame). Take the overpass (head east, over Highway 101) and turn right to the hotel.

If you are traveling north on Highway 101 toward the airport, take the Broadway/Burlingame exit (before you reach the airport) and turn right to the hotel.

For further information contact

Dr. Purabi Mazumdar
ATP/NIST
Telephone: 301-975-4891
Fax: 301-926-9524
E-mail: purabi.muzumdar@nist.gov
Date created: October 1997
Last updated: May 6, 2003
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